The Field Programmable Gate Array or FPGA is a semiconductor device comprising of logic blocks programmed to execute a specific set of functions. These logic blocks are connected helping of an interconnect matrix. The structure is in the form of two-dimensional array consist of logic blocks, interconnects connecting it with input and output signals. One of the benefits of FPGA is they are reprogrammable to modify serving a function that is different from the one they perform.
If you want to learn about FPGA design flow, then below are the steps-
- Design Entry
Design entry is done using various techniques like schematics, through Hardware Description Language or HDL. This design deals with more complex systems and it is better to opt for HDL. Design entry has a schematic based technique, which is easy to read and comprehend.
Once the design is entered in the form of code, this phase is translated into an actual circuit with elements like gates, flip-flops, and multipliers among others. The input HDL is converted into a netlist, which lists the logic elements you will need for the project.
This phase involves the layout of the design determining three steps- Translate, Map, and Place & Route. The tools used provided by FPGA because they know the best how to translate synthesized netlist into FPGA.
- Timing Verification
You can verify the timing of the design at different points. You can verify in two ways-
* Run static timing analysis through- After Map and After Place & Route
* Run Timing Simulation- For partial timing analysis of CLB and IOB delays
* After Place and Route (for full-timing analysis of block and net delays
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